Intel has officially outlined the roadmap for its upcoming robotics and edge AI platform, confirming that the Razor Lake-AX system-on-chip will officially ship in 2028. Revealed during the Semiconductors Powering Humanoids summit by Intel senior vice president Cho Min-sung, the specialized processor is designed specifically for autonomous mobile robots and humanoid robotics rather than conventional desktop computing markets.

Architecture and Compute Capabilities

The Razor Lake-AX architecture centers on delivering up to 700 TOPS of on-die AI compute power. This performance figure represents a substantial generational leap, scaling to approximately 3.88 times the 180 TOPS output found in current Panther Lake Core Series 3 hardware.

To support heavy neural network workloads alongside real-time control systems, the SoC incorporates a large integrated Xe3 graphics processing unit configured in either 16-core or 32-core architectural variants. Hardware integration further extends to on-package LPDDR5X and LPDDR6 memory housed within a massive BGA-4326 physical package utilizing 4,326 individual pins.

Despite the official disclosures regarding packaging and compute metrics, Intel has not yet released complete technical specifications. Exact power consumption targets, the specific CPU core mix regarding performance and efficiency cores, and total memory capacity remain unconfirmed by company leadership.

Platform Positioning and Roadmap Context

Positioned squarely for high-performance edge AI and advanced humanoid robotics, Razor Lake-AX represents a targeted departure from consumer-grade computing lines. Industry observers note that this platform follows Intel's broader roadmap strategy, which includes the anticipated introduction of the Nova Lake platform slated as a robotics platform for 2027.

Hardware analysis indicates that the physical implementation relies heavily on advanced manufacturing methodologies. Specifically, the processor utilizes sophisticated packaging technologies including EMIB and Foveros 3D to integrate diverse compute elements, alongside an estimated integrated GPU die size of approximately 162.84 square millimeters.

While these advanced packaging methods outline how Intel plans to physically construct the silicon, system integrators must still account for significant unknowns before final deployment. Beyond the unverified thermal thresholds and missing core distribution counts, commercial pricing models and specific target device categories outside of ambulatory robotics have not been finalized or publicized by the manufacturer. These limitations mean prospective deployers cannot yet model exact power delivery networks or cooling requirements for chassis integration.

For developers and system integrators tracking these developments, critical missing parameters include finalized pricing structures, specific target device categories outside of autonomous robotics, and exact thermal design power thresholds. These operational metrics will dictate how effectively the hardware meets the rigorous demands of real-time mobile environments.

The next confirmed milestone for Intel's robotics hardware division involves pre-production sampling and further technical disclosures leading up to the broader 2028 commercial availability window confirmed at the recent summit.